-#define URM_RX_FIFO_RESET_0 0x018
-#define URM_RX_FIFO_RESET_1 0x019
-#define URM_RX_FIFO_RESET_2 0x01a
-#define URM_RX_FIFO_RESET_3 0x01b
-#define URM_TX_FIFO_RESET_0 0x01c
-#define URM_TX_FIFO_RESET_1 0x01d
-#define URM_TX_FIFO_RESET_2 0x01e
-#define URM_TX_FIFO_RESET_3 0x01f
-
-
-#define RAMCTL_REGS_TXFIFO_0_LEVEL 0x000
-#define RAMCTL_REGS_TXFIFO_1_LEVEL 0x001
-#define RAMCTL_REGS_TXFIFO_2_LEVEL 0x002
-#define RAMCTL_REGS_TXFIFO_3_LEVEL 0x003
-#define RAMCTL_REGS_RXFIFO_0_LEVEL 0x004
-
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_M 0x7ff
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_S 0
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL 0x7ff
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_M 0x1
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_S 11
-#define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE 0x800
-
-#define RAMCTL_REGS_RXFIFO_1_LEVEL 0x005
-#define RAMCTL_REGS_RXFIFO_2_LEVEL 0x006
-#define RAMCTL_REGS_RXFIFO_3_LEVEL 0x007
-
-#define RAMCTL_BUFFER_PARITY 0x1
-#define RAMCTL_BUFFER_BREAK 0x2
-#define RAMCTL_BUFFER_FRAME 0x4
-#define RAMCTL_BUFFER_OVERRUN 0x8
-