7 #define UART_0_REG_BLOCK 0
8 #define UART_1_REG_BLOCK 1
9 #define UART_2_REG_BLOCK 2
10 #define UART_3_REG_BLOCK 3
11 #define URM_REG_BLOCK 4
12 #define PRM_REG_BLOCK 5
13 #define EPMERR_REG_BLOCK 6
14 #define RAMCTL_REG_BLOCK 0x64
15 #define TWI_ROM_REG_BLOCK 0x65
16 #define EPLOCALS_REG_BLOCK 0x66
18 #define MEM_SHADOW_REG_SIZE_S 5
19 #define MEM_SHADOW_REG_SIZE (1 << MEM_SHADOW_REG_SIZE_S)
21 #define MEM_EP_LOCALS_SIZE_S 3
22 #define MEM_EP_LOCALS_SIZE (1 << MEM_EP_LOCALS_SIZE_S)
24 #define EP_WIDE_MODE 0x03
27 #define UART_GPIO_MODE 0x01a
29 #define UART_GPIO_MODE_SEL_M 0x7
30 #define UART_GPIO_MODE_SEL_S 0
31 #define UART_GPIO_MODE_SEL 0x007
33 #define UART_GPIO_MODE_SEL_GPIO (0x0 << UART_GPIO_MODE_SEL_S)
34 #define UART_GPIO_MODE_SEL_RTS_CTS (0x1 << UART_GPIO_MODE_SEL_S)
35 #define UART_GPIO_MODE_SEL_DTR_DSR (0x2 << UART_GPIO_MODE_SEL_S)
36 #define UART_GPIO_MODE_SEL_XCVR_EN_ACT (0x3 << UART_GPIO_MODE_SEL_S)
37 #define UART_GPIO_MODE_SEL_XCVR_EN_FLOW (0x4 << UART_GPIO_MODE_SEL_S)
39 #define UART_GPIO_MODE_XCVR_EN_POL_M 0x1
40 #define UART_GPIO_MODE_XCVR_EN_POL_S 3
41 #define UART_GPIO_MODE_XCVR_EN_POL 0x008
43 #define UART_ENABLE 0x003
44 #define UART_ENABLE_TX_M 0x1
45 #define UART_ENABLE_TX_S 0
46 #define UART_ENABLE_TX 0x001
47 #define UART_ENABLE_RX_M 0x1
48 #define UART_ENABLE_RX_S 1
49 #define UART_ENABLE_RX 0x002
51 #define UART_CLOCK_DIVISOR_0 0x004
52 #define UART_CLOCK_DIVISOR_1 0x005
53 #define UART_CLOCK_DIVISOR_2 0x006
55 #define UART_CLOCK_DIVISOR_2_MSB_M 0x7
56 #define UART_CLOCK_DIVISOR_2_MSB_S 0
57 #define UART_CLOCK_DIVISOR_2_MSB 0x007
58 #define UART_CLOCK_DIVISOR_2_DIAGMODE_M 0x1
59 #define UART_CLOCK_DIVISOR_2_DIAGMODE_S 3
60 #define UART_CLOCK_DIVISOR_2_DIAGMODE 0x008
62 #define UART_TX_CLOCK_MASK_0 0x007
63 #define UART_TX_CLOCK_MASK_1 0x008
65 #define UART_RX_CLOCK_MASK_0 0x009
66 #define UART_RX_CLOCK_MASK_1 0x00a
68 #define UART_FORMAT 0x00b
70 #define UART_FORMAT_SIZE_M 0xf
71 #define UART_FORMAT_SIZE_S 0
72 #define UART_FORMAT_SIZE 0x00f
74 #define UART_FORMAT_SIZE_7 (0x7 << UART_FORMAT_SIZE_S)
75 #define UART_FORMAT_SIZE_8 (0x8 << UART_FORMAT_SIZE_S)
76 #define UART_FORMAT_SIZE_9 (0x9 << UART_FORMAT_SIZE_S)
78 #define UART_FORMAT_PARITY_M 0x7
79 #define UART_FORMAT_PARITY_S 4
80 #define UART_FORMAT_PARITY 0x070
82 #define UART_FORMAT_PARITY_NONE (0x0 << UART_FORMAT_PARITY_S)
83 #define UART_FORMAT_PARITY_ODD (0x1 << UART_FORMAT_PARITY_S)
84 #define UART_FORMAT_PARITY_EVEN (0x2 << UART_FORMAT_PARITY_S)
85 #define UART_FORMAT_PARITY_1 (0x3 << UART_FORMAT_PARITY_S)
86 #define UART_FORMAT_PARITY_0 (0x4 << UART_FORMAT_PARITY_S)
88 #define UART_FORMAT_STOP_M 0x1
89 #define UART_FORMAT_STOP_S 7
90 #define UART_FORMAT_STOP 0x080
92 #define UART_FORMAT_STOP_1 (0x0 << UART_FORMAT_STOP_S)
93 #define UART_FORMAT_STOP_2 (0x1 << UART_FORMAT_STOP_S)
95 #define UART_FORMAT_MODE_7N1 0
96 #define UART_FORMAT_MODE_RES1 1
97 #define UART_FORMAT_MODE_RES2 2
98 #define UART_FORMAT_MODE_RES3 3
99 #define UART_FORMAT_MODE_7N2 4
100 #define UART_FORMAT_MODE_7P1 5
101 #define UART_FORMAT_MODE_8N1 6
102 #define UART_FORMAT_MODE_RES7 7
103 #define UART_FORMAT_MODE_7P2 8
104 #define UART_FORMAT_MODE_8N2 9
105 #define UART_FORMAT_MODE_8P1 10
106 #define UART_FORMAT_MODE_9N1 11
107 #define UART_FORMAT_MODE_8P2 12
108 #define UART_FORMAT_MODE_RESD 13
109 #define UART_FORMAT_MODE_RESE 14
110 #define UART_FORMAT_MODE_9N2 15
112 #define UART_FLOW 0x00c
114 #define UART_FLOW_MODE_M 0x7
115 #define UART_FLOW_MODE_S 0
116 #define UART_FLOW_MODE 0x007
118 #define UART_FLOW_MODE_NONE (0x0 << UART_FLOW_MODE_S)
119 #define UART_FLOW_MODE_HW (0x1 << UART_FLOW_MODE_S)
120 #define UART_FLOW_MODE_SW (0x2 << UART_FLOW_MODE_S)
121 #define UART_FLOW_MODE_ADDR_MATCH (0x3 << UART_FLOW_MODE_S)
122 #define UART_FLOW_MODE_ADDR_MATCH_TX (0x4 << UART_FLOW_MODE_S)
124 #define UART_FLOW_HALF_DUPLEX_M 0x1
125 #define UART_FLOW_HALF_DUPLEX_S 3
126 #define UART_FLOW_HALF_DUPLEX 0x008
128 #define UART_LOOPBACK_CTL 0x012
129 #define UART_LOOPBACK_CTL_ENABLE_M 0x1
130 #define UART_LOOPBACK_CTL_ENABLE_S 2
131 #define UART_LOOPBACK_CTL_ENABLE 0x004
132 #define UART_LOOPBACK_CTL_RX_SOURCE_M 0x3
133 #define UART_LOOPBACK_CTL_RX_SOURCE_S 0
134 #define UART_LOOPBACK_CTL_RX_SOURCE 0x003
135 #define UART_LOOPBACK_CTL_RX_UART0 (0x0 << UART_LOOPBACK_CTL_RX_SOURCE_S)
136 #define UART_LOOPBACK_CTL_RX_UART1 (0x1 << UART_LOOPBACK_CTL_RX_SOURCE_S)
137 #define UART_LOOPBACK_CTL_RX_UART2 (0x2 << UART_LOOPBACK_CTL_RX_SOURCE_S)
138 #define UART_LOOPBACK_CTL_RX_UART3 (0x3 << UART_LOOPBACK_CTL_RX_SOURCE_S)
140 #define UART_CHANNEL_NUM 0x00d
142 #define UART_XON_CHAR 0x010
143 #define UART_XOFF_CHAR 0x011
145 #define UART_GPIO_SET 0x01d
146 #define UART_GPIO_CLR 0x01e
147 #define UART_GPIO_STATUS 0x01f
149 #define URM_ENABLE_BASE 0x010
150 #define URM_ENABLE_0 0x010
151 #define URM_ENABLE_0_TX_M 0x1
152 #define URM_ENABLE_0_TX_S 0
153 #define URM_ENABLE_0_TX 0x001
154 #define URM_ENABLE_0_RX_M 0x1
155 #define URM_ENABLE_0_RX_S 1
156 #define URM_ENABLE_0_RX 0x002
158 #define URM_RX_FIFO_RESET_0 0x018
159 #define URM_RX_FIFO_RESET_1 0x019
160 #define URM_RX_FIFO_RESET_2 0x01a
161 #define URM_RX_FIFO_RESET_3 0x01b
162 #define URM_TX_FIFO_RESET_0 0x01c
163 #define URM_TX_FIFO_RESET_1 0x01d
164 #define URM_TX_FIFO_RESET_2 0x01e
165 #define URM_TX_FIFO_RESET_3 0x01f
168 #define RAMCTL_REGS_TXFIFO_0_LEVEL 0x000
169 #define RAMCTL_REGS_TXFIFO_1_LEVEL 0x001
170 #define RAMCTL_REGS_TXFIFO_2_LEVEL 0x002
171 #define RAMCTL_REGS_TXFIFO_3_LEVEL 0x003
172 #define RAMCTL_REGS_RXFIFO_0_LEVEL 0x004
174 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_M 0x7ff
175 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_S 0
176 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL 0x7ff
177 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_M 0x1
178 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_S 11
179 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE 0x800
181 #define RAMCTL_REGS_RXFIFO_1_LEVEL 0x005
182 #define RAMCTL_REGS_RXFIFO_2_LEVEL 0x006
183 #define RAMCTL_REGS_RXFIFO_3_LEVEL 0x007
185 #define RAMCTL_BUFFER_PARITY 0x1
186 #define RAMCTL_BUFFER_BREAK 0x2
187 #define RAMCTL_BUFFER_FRAME 0x4
188 #define RAMCTL_BUFFER_OVERRUN 0x8
195 * Major and minor numbers.
198 #define ACM_TTY_MAJOR 166
199 #define ACM_TTY_MINORS 256
205 #define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
208 * Output control lines.
211 #define ACM_CTRL_DTR 0x01
212 #define ACM_CTRL_RTS 0x02
215 * Input control lines and line errors.
218 #define ACM_CTRL_DCD 0x01
219 #define ACM_CTRL_DSR 0x02
220 #define ACM_CTRL_BRK 0x04
221 #define ACM_CTRL_RI 0x08
223 #define ACM_CTRL_FRAMING 0x10
224 #define ACM_CTRL_PARITY 0x20
225 #define ACM_CTRL_OVERRUN 0x40
228 * Internal driver structures.
232 * The only reason to have several buffers is to accommodate assumptions
233 * in line disciplines. They ask for empty space amount, receive our URB size,
234 * and proceed to issue several 1-character writes, assuming they will fit.
235 * The very first write takes a complete URB. Fortunately, this only happens
236 * when processing onlcr, so we only need 2 buffers. These values must be
248 struct acm *instance;
256 struct acm *instance;
260 struct usb_device *dev; /* the corresponding usb device */
261 struct usb_interface *control; /* control interface */
262 struct usb_interface *data; /* data interface */
263 struct tty_port port; /* our tty port data */
264 struct urb *ctrlurb; /* urbs */
265 u8 *ctrl_buffer; /* buffers of urbs */
266 dma_addr_t ctrl_dma; /* dma handles of buffers */
267 u8 *country_codes; /* country codes from device */
268 unsigned int country_code_size; /* size of this buffer */
269 unsigned int country_rel_date; /* release date of version */
270 struct acm_wb wb[ACM_NW];
271 unsigned long read_urbs_free;
272 struct urb *read_urbs[ACM_NR];
273 struct acm_rb read_buffers[ACM_NR];
276 spinlock_t read_lock;
277 int write_used; /* number of non-empty write buffers */
279 spinlock_t write_lock;
282 struct usb_cdc_line_coding line; /* bits, stop, parity */
283 struct work_struct work; /* work queue entry for line discipline waking up */
284 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
285 unsigned int ctrlout; /* output control lines (DTR, RTS) */
286 struct async_icount iocount; /* counters for control line changes */
287 struct async_icount oldcount; /* for comparison of counter */
288 wait_queue_head_t wioctl; /* for ioctl */
289 unsigned int writesize; /* max packet size for the output bulk endpoint */
290 unsigned int readsize,ctrlsize; /* buffer sizes for freeing */
291 unsigned int minor; /* acm minor number */
292 unsigned char clocal; /* termios CLOCAL */
293 unsigned int ctrl_caps; /* control capabilities from the class specific header */
294 unsigned int susp_count; /* number of suspended interfaces */
295 unsigned int combined_interfaces:1; /* control and data collapsed */
296 unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */
297 unsigned int throttled:1; /* actually throttled */
298 unsigned int throttle_req:1; /* throttle requested */
300 struct usb_anchor delayed; /* writes queued for a device about to be woken */
301 unsigned long quirks;
304 int preciseflags; /* USB: wide mode, TTY: flags per character */
305 int trans9; /* USB: wide mode, serial 9N1 */
313 #define CDC_DATA_INTERFACE_TYPE 0x0a
315 /* constants describing various quirks and errors */
316 #define NO_UNION_NORMAL BIT(0)
317 #define SINGLE_RX_URB BIT(1)
318 #define NO_CAP_LINE BIT(2)
319 #define NO_DATA_INTERFACE BIT(4)
320 #define IGNORE_DEVICE BIT(5)
321 #define QUIRK_CONTROL_LINE_STATE BIT(6)
322 #define CLEAR_HALT_CONDITIONS BIT(7)