vizzini.h

   1 #ifndef VIZZINI_H
   2 #define VIZZINI_H
   3
   4 #define XR_SET_REG              0
   5
   6 #define URM_REG_BLOCK           4
   7 #define EPLOCALS_REG_BLOCK      0x66
   8
   9 #define MEM_EP_LOCALS_SIZE_S    3
  10 #define MEM_EP_LOCALS_SIZE      (1 << MEM_EP_LOCALS_SIZE_S)
  11
  12 #define EP_WIDE_MODE            0x03
  13
  14
  15 #define UART_GPIO_MODE                                     0x01a
  16
  17 #define UART_GPIO_MODE_SEL_M                               0x7
  18 #define UART_GPIO_MODE_SEL_S                               0
  19 #define UART_GPIO_MODE_SEL                                 0x007
  20
  21 #define UART_GPIO_MODE_SEL_GPIO                            (0x0 << UART_GPIO_MODE_SEL_S)
  22 #define UART_GPIO_MODE_SEL_RTS_CTS                         (0x1 << UART_GPIO_MODE_SEL_S)
  23 #define UART_GPIO_MODE_SEL_DTR_DSR                         (0x2 << UART_GPIO_MODE_SEL_S)
  24
  25 #define UART_ENABLE                                        0x003
  26 #define UART_ENABLE_TX_M                                   0x1
  27 #define UART_ENABLE_TX_S                                   0
  28 #define UART_ENABLE_TX                                     0x001
  29 #define UART_ENABLE_RX_M                                   0x1
  30 #define UART_ENABLE_RX_S                                   1
  31 #define UART_ENABLE_RX                                     0x002
  32
  33 #define UART_CLOCK_DIVISOR_0                               0x004
  34 #define UART_CLOCK_DIVISOR_1                               0x005
  35 #define UART_CLOCK_DIVISOR_2                               0x006
  36
  37 #define UART_TX_CLOCK_MASK_0                               0x007
  38 #define UART_TX_CLOCK_MASK_1                               0x008
  39
  40 #define UART_RX_CLOCK_MASK_0                               0x009
  41 #define UART_RX_CLOCK_MASK_1                               0x00a
  42
  43 #define UART_FORMAT                                        0x00b
  44
  45 #define UART_FORMAT_SIZE_M                                 0xf
  46 #define UART_FORMAT_SIZE_S                                 0
  47 #define UART_FORMAT_SIZE                                   0x00f
  48
  49 #define UART_FORMAT_SIZE_7                                 (0x7 << UART_FORMAT_SIZE_S)
  50 #define UART_FORMAT_SIZE_8                                 (0x8 << UART_FORMAT_SIZE_S)
  51 #define UART_FORMAT_SIZE_9                                 (0x9 << UART_FORMAT_SIZE_S)
  52
  53 #define UART_FORMAT_PARITY_M                               0x7
  54 #define UART_FORMAT_PARITY_S                               4
  55 #define UART_FORMAT_PARITY                                 0x070
  56
  57 #define UART_FORMAT_PARITY_NONE                            (0x0 << UART_FORMAT_PARITY_S)
  58 #define UART_FORMAT_PARITY_ODD                             (0x1 << UART_FORMAT_PARITY_S)
  59 #define UART_FORMAT_PARITY_EVEN                            (0x2 << UART_FORMAT_PARITY_S)
  60 #define UART_FORMAT_PARITY_1                               (0x3 << UART_FORMAT_PARITY_S)
  61 #define UART_FORMAT_PARITY_0                               (0x4 << UART_FORMAT_PARITY_S)
  62
  63 #define UART_FORMAT_STOP_M                                 0x1
  64 #define UART_FORMAT_STOP_S                                 7
  65 #define UART_FORMAT_STOP                                   0x080
  66
  67 #define UART_FORMAT_STOP_1                                 (0x0 << UART_FORMAT_STOP_S)
  68 #define UART_FORMAT_STOP_2                                 (0x1 << UART_FORMAT_STOP_S)
  69
  70 #define UART_FLOW                                          0x00c
  71
  72 #define UART_FLOW_MODE_M                                   0x7
  73 #define UART_FLOW_MODE_S                                   0
  74 #define UART_FLOW_MODE                                     0x007
  75
  76 #define UART_FLOW_MODE_NONE                                (0x0 << UART_FLOW_MODE_S)
  77 #define UART_FLOW_MODE_HW                                  (0x1 << UART_FLOW_MODE_S)
  78 #define UART_FLOW_MODE_SW                                  (0x2 << UART_FLOW_MODE_S)
  79
  80 #define UART_XON_CHAR                                      0x010
  81 #define UART_XOFF_CHAR                                     0x011
  82
  83 #define URM_ENABLE_BASE                                    0x010
  84 #define URM_ENABLE_0                                       0x010
  85 #define URM_ENABLE_0_TX                                    0x001
  86 #define URM_ENABLE_0_RX                                    0x002
  87
  88 #ifndef CMSPAR
  89 #define CMSPAR                  0
  90 #endif
  91
  92 /*
  93  * Major and minor numbers.
  94  */
  95
  96 #define ACM_TTY_MAJOR           166
  97 #define ACM_TTY_MINORS          256
  98
  99 /*
 100  * Requests.
 101  */
 102
 103 #define USB_RT_ACM              (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
 104
 105 /*
 106  * Output control lines.
 107  */
 108
 109 #define ACM_CTRL_DTR            0x01
 110 #define ACM_CTRL_RTS            0x02
 111
 112 /*
 113  * Input control lines and line errors.
 114  */
 115
 116 #define ACM_CTRL_DCD            0x01
 117 #define ACM_CTRL_DSR            0x02
 118 #define ACM_CTRL_BRK            0x04
 119 #define ACM_CTRL_RI             0x08
 120
 121 #define ACM_CTRL_FRAMING        0x10
 122 #define ACM_CTRL_PARITY         0x20
 123 #define ACM_CTRL_OVERRUN        0x40
 124
 125 /*
 126  * Internal driver structures.
 127  */
 128
 129 /*
 130  * The only reason to have several buffers is to accommodate assumptions
 131  * in line disciplines. They ask for empty space amount, receive our URB size,
 132  * and proceed to issue several 1-character writes, assuming they will fit.
 133  * The very first write takes a complete URB. Fortunately, this only happens
 134  * when processing onlcr, so we only need 2 buffers. These values must be
 135  * powers of 2.
 136  */
 137 #define ACM_NW  16
 138 #define ACM_NR  16
 139
 140 struct acm_wb {
 141         unsigned char *buf;
 142         dma_addr_t dmah;
 143         int len;
 144         int use;
 145         struct urb              *urb;
 146         struct acm              *instance;
 147 };
 148
 149 struct acm_rb {
 150         int                     size;
 151         unsigned char           *base;
 152         dma_addr_t              dma;
 153         int                     index;
 154         struct acm              *instance;
 155 };
 156
 157 struct acm {
 158         struct usb_device *dev;                         /* the corresponding usb device */
 159         struct usb_interface *control;                  /* control interface */
 160         struct usb_interface *data;                     /* data interface */
 161         struct tty_port port;                           /* our tty port data */
 162         struct urb *ctrlurb;                            /* urbs */
 163         u8 *ctrl_buffer;                                /* buffers of urbs */
 164         dma_addr_t ctrl_dma;                            /* dma handles of buffers */
 165         u8 *country_codes;                              /* country codes from device */
 166         unsigned int country_code_size;                 /* size of this buffer */
 167         unsigned int country_rel_date;                  /* release date of version */
 168         struct acm_wb wb[ACM_NW];
 169         unsigned long read_urbs_free;
 170         struct urb *read_urbs[ACM_NR];
 171         struct acm_rb read_buffers[ACM_NR];
 172         int rx_buflimit;
 173         int rx_endpoint;
 174         spinlock_t read_lock;
 175         int write_used;                                 /* number of non-empty write buffers */
 176         int transmitting;
 177         spinlock_t write_lock;
 178         struct mutex mutex;
 179         bool disconnected;
 180         struct usb_cdc_line_coding line;                /* bits, stop, parity */
 181         struct work_struct work;                        /* work queue entry for line discipline waking up */
 182         unsigned int ctrlin;                            /* input control lines (DCD, DSR, RI, break, overruns) */
 183         unsigned int ctrlout;                           /* output control lines (DTR, RTS) */
 184         struct async_icount iocount;                    /* counters for control line changes */
 185         struct async_icount oldcount;                   /* for comparison of counter */
 186         wait_queue_head_t wioctl;                       /* for ioctl */
 187         unsigned int writesize;                         /* max packet size for the output bulk endpoint */
 188         unsigned int readsize,ctrlsize;                 /* buffer sizes for freeing */
 189         unsigned int minor;                             /* acm minor number */
 190         unsigned char clocal;                           /* termios CLOCAL */
 191         unsigned int ctrl_caps;                         /* control capabilities from the class specific header */
 192         unsigned int susp_count;                        /* number of suspended interfaces */
 193         unsigned int combined_interfaces:1;             /* control and data collapsed */
 194         unsigned int is_int_ep:1;                       /* interrupt endpoints contrary to spec used */
 195         unsigned int throttled:1;                       /* actually throttled */
 196         unsigned int throttle_req:1;                    /* throttle requested */
 197         u8 bInterval;
 198         struct usb_anchor delayed;                      /* writes queued for a device about to be woken */
 199         unsigned long quirks;
 200
 201         int           block;
 202         int           preciseflags; /* USB: wide mode, TTY: flags per character */
 203         int           trans9;   /* USB: wide mode, serial 9N1 */
 204
 205 };
 206
 207 #define CDC_DATA_INTERFACE_TYPE 0x0a
 208
 209 /* constants describing various quirks and errors */
 210 #define NO_UNION_NORMAL                 BIT(0)
 211 #define SINGLE_RX_URB                   BIT(1)
 212 #define NO_CAP_LINE                     BIT(2)
 213 #define NO_DATA_INTERFACE               BIT(4)
 214 #define IGNORE_DEVICE                   BIT(5)
 215 #define QUIRK_CONTROL_LINE_STATE        BIT(6)
 216 #define CLEAR_HALT_CONDITIONS           BIT(7)
 217
 218 #endif /*VIZZINI_H*/