vizzini.h

   1 #ifndef VIZZINI_H
   2 #define VIZZINI_H
   3
   4 #define XR_SET_REG              0
   5 #define XR_GETN_REG             1
   6
   7 #define UART_0_REG_BLOCK        0
   8 #define UART_1_REG_BLOCK        1
   9 #define UART_2_REG_BLOCK        2
  10 #define UART_3_REG_BLOCK        3
  11 #define URM_REG_BLOCK           4
  12 #define PRM_REG_BLOCK           5
  13 #define EPMERR_REG_BLOCK        6
  14 #define RAMCTL_REG_BLOCK        0x64
  15 #define TWI_ROM_REG_BLOCK       0x65
  16 #define EPLOCALS_REG_BLOCK      0x66
  17
  18 #define MEM_SHADOW_REG_SIZE_S   5
  19 #define MEM_SHADOW_REG_SIZE     (1 << MEM_SHADOW_REG_SIZE_S)
  20
  21 #define MEM_EP_LOCALS_SIZE_S    3
  22 #define MEM_EP_LOCALS_SIZE      (1 << MEM_EP_LOCALS_SIZE_S)
  23
  24 #define EP_WIDE_MODE            0x03
  25
  26
  27 #define UART_GPIO_MODE                                     0x01a
  28
  29 #define UART_GPIO_MODE_SEL_M                               0x7
  30 #define UART_GPIO_MODE_SEL_S                               0
  31 #define UART_GPIO_MODE_SEL                                 0x007
  32
  33 #define UART_GPIO_MODE_SEL_GPIO                            (0x0 << UART_GPIO_MODE_SEL_S)
  34 #define UART_GPIO_MODE_SEL_RTS_CTS                         (0x1 << UART_GPIO_MODE_SEL_S)
  35 #define UART_GPIO_MODE_SEL_DTR_DSR                         (0x2 << UART_GPIO_MODE_SEL_S)
  36 #define UART_GPIO_MODE_SEL_XCVR_EN_ACT                     (0x3 << UART_GPIO_MODE_SEL_S)
  37 #define UART_GPIO_MODE_SEL_XCVR_EN_FLOW                    (0x4 << UART_GPIO_MODE_SEL_S)
  38
  39 #define UART_GPIO_MODE_XCVR_EN_POL_M                       0x1
  40 #define UART_GPIO_MODE_XCVR_EN_POL_S                       3
  41 #define UART_GPIO_MODE_XCVR_EN_POL                         0x008
  42
  43 #define UART_ENABLE                                        0x003
  44 #define UART_ENABLE_TX_M                                   0x1
  45 #define UART_ENABLE_TX_S                                   0
  46 #define UART_ENABLE_TX                                     0x001
  47 #define UART_ENABLE_RX_M                                   0x1
  48 #define UART_ENABLE_RX_S                                   1
  49 #define UART_ENABLE_RX                                     0x002
  50
  51 #define UART_CLOCK_DIVISOR_0                               0x004
  52 #define UART_CLOCK_DIVISOR_1                               0x005
  53 #define UART_CLOCK_DIVISOR_2                               0x006
  54
  55 #define UART_CLOCK_DIVISOR_2_MSB_M                         0x7
  56 #define UART_CLOCK_DIVISOR_2_MSB_S                         0
  57 #define UART_CLOCK_DIVISOR_2_MSB                           0x007
  58 #define UART_CLOCK_DIVISOR_2_DIAGMODE_M                    0x1
  59 #define UART_CLOCK_DIVISOR_2_DIAGMODE_S                    3
  60 #define UART_CLOCK_DIVISOR_2_DIAGMODE                      0x008
  61
  62 #define UART_TX_CLOCK_MASK_0                               0x007
  63 #define UART_TX_CLOCK_MASK_1                               0x008
  64
  65 #define UART_RX_CLOCK_MASK_0                               0x009
  66 #define UART_RX_CLOCK_MASK_1                               0x00a
  67
  68 #define UART_FORMAT                                        0x00b
  69
  70 #define UART_FORMAT_SIZE_M                                 0xf
  71 #define UART_FORMAT_SIZE_S                                 0
  72 #define UART_FORMAT_SIZE                                   0x00f
  73
  74 #define UART_FORMAT_SIZE_7                                 (0x7 << UART_FORMAT_SIZE_S)
  75 #define UART_FORMAT_SIZE_8                                 (0x8 << UART_FORMAT_SIZE_S)
  76 #define UART_FORMAT_SIZE_9                                 (0x9 << UART_FORMAT_SIZE_S)
  77
  78 #define UART_FORMAT_PARITY_M                               0x7
  79 #define UART_FORMAT_PARITY_S                               4
  80 #define UART_FORMAT_PARITY                                 0x070
  81
  82 #define UART_FORMAT_PARITY_NONE                            (0x0 << UART_FORMAT_PARITY_S)
  83 #define UART_FORMAT_PARITY_ODD                             (0x1 << UART_FORMAT_PARITY_S)
  84 #define UART_FORMAT_PARITY_EVEN                            (0x2 << UART_FORMAT_PARITY_S)
  85 #define UART_FORMAT_PARITY_1                               (0x3 << UART_FORMAT_PARITY_S)
  86 #define UART_FORMAT_PARITY_0                               (0x4 << UART_FORMAT_PARITY_S)
  87
  88 #define UART_FORMAT_STOP_M                                 0x1
  89 #define UART_FORMAT_STOP_S                                 7
  90 #define UART_FORMAT_STOP                                   0x080
  91
  92 #define UART_FORMAT_STOP_1                                 (0x0 << UART_FORMAT_STOP_S)
  93 #define UART_FORMAT_STOP_2                                 (0x1 << UART_FORMAT_STOP_S)
  94
  95 #define UART_FORMAT_MODE_7N1                               0
  96 #define UART_FORMAT_MODE_RES1                              1
  97 #define UART_FORMAT_MODE_RES2                              2
  98 #define UART_FORMAT_MODE_RES3                              3
  99 #define UART_FORMAT_MODE_7N2                               4
 100 #define UART_FORMAT_MODE_7P1                               5
 101 #define UART_FORMAT_MODE_8N1                               6
 102 #define UART_FORMAT_MODE_RES7                              7
 103 #define UART_FORMAT_MODE_7P2                               8
 104 #define UART_FORMAT_MODE_8N2                               9
 105 #define UART_FORMAT_MODE_8P1                               10
 106 #define UART_FORMAT_MODE_9N1                               11
 107 #define UART_FORMAT_MODE_8P2                               12
 108 #define UART_FORMAT_MODE_RESD                              13
 109 #define UART_FORMAT_MODE_RESE                              14
 110 #define UART_FORMAT_MODE_9N2                               15
 111
 112 #define UART_FLOW                                          0x00c
 113
 114 #define UART_FLOW_MODE_M                                   0x7
 115 #define UART_FLOW_MODE_S                                   0
 116 #define UART_FLOW_MODE                                     0x007
 117
 118 #define UART_FLOW_MODE_NONE                                (0x0 << UART_FLOW_MODE_S)
 119 #define UART_FLOW_MODE_HW                                  (0x1 << UART_FLOW_MODE_S)
 120 #define UART_FLOW_MODE_SW                                  (0x2 << UART_FLOW_MODE_S)
 121 #define UART_FLOW_MODE_ADDR_MATCH                          (0x3 << UART_FLOW_MODE_S)
 122 #define UART_FLOW_MODE_ADDR_MATCH_TX                       (0x4 << UART_FLOW_MODE_S)
 123
 124 #define UART_FLOW_HALF_DUPLEX_M                            0x1
 125 #define UART_FLOW_HALF_DUPLEX_S                            3
 126 #define UART_FLOW_HALF_DUPLEX                              0x008
 127
 128 #define UART_LOOPBACK_CTL                                  0x012
 129 #define UART_LOOPBACK_CTL_ENABLE_M                         0x1
 130 #define UART_LOOPBACK_CTL_ENABLE_S                         2
 131 #define UART_LOOPBACK_CTL_ENABLE                           0x004
 132 #define UART_LOOPBACK_CTL_RX_SOURCE_M                      0x3
 133 #define UART_LOOPBACK_CTL_RX_SOURCE_S                      0
 134 #define UART_LOOPBACK_CTL_RX_SOURCE                        0x003
 135 #define UART_LOOPBACK_CTL_RX_UART0                         (0x0 << UART_LOOPBACK_CTL_RX_SOURCE_S)
 136 #define UART_LOOPBACK_CTL_RX_UART1                         (0x1 << UART_LOOPBACK_CTL_RX_SOURCE_S)
 137 #define UART_LOOPBACK_CTL_RX_UART2                         (0x2 << UART_LOOPBACK_CTL_RX_SOURCE_S)
 138 #define UART_LOOPBACK_CTL_RX_UART3                         (0x3 << UART_LOOPBACK_CTL_RX_SOURCE_S)
 139
 140 #define UART_CHANNEL_NUM                                   0x00d
 141
 142 #define UART_XON_CHAR                                      0x010
 143 #define UART_XOFF_CHAR                                     0x011
 144
 145 #define UART_GPIO_SET                                      0x01d
 146 #define UART_GPIO_CLR                                      0x01e
 147 #define UART_GPIO_STATUS                                   0x01f
 148
 149 #define URM_ENABLE_BASE                                    0x010
 150 #define URM_ENABLE_0                                       0x010
 151 #define URM_ENABLE_0_TX_M                                  0x1
 152 #define URM_ENABLE_0_TX_S                                  0
 153 #define URM_ENABLE_0_TX                                    0x001
 154 #define URM_ENABLE_0_RX_M                                  0x1
 155 #define URM_ENABLE_0_RX_S                                  1
 156 #define URM_ENABLE_0_RX                                    0x002
 157
 158 #define URM_RX_FIFO_RESET_0                                0x018
 159 #define URM_RX_FIFO_RESET_1                                0x019
 160 #define URM_RX_FIFO_RESET_2                                0x01a
 161 #define URM_RX_FIFO_RESET_3                                0x01b
 162 #define URM_TX_FIFO_RESET_0                                0x01c
 163 #define URM_TX_FIFO_RESET_1                                0x01d
 164 #define URM_TX_FIFO_RESET_2                                0x01e
 165 #define URM_TX_FIFO_RESET_3                                0x01f
 166
 167
 168 #define RAMCTL_REGS_TXFIFO_0_LEVEL                         0x000
 169 #define RAMCTL_REGS_TXFIFO_1_LEVEL                         0x001
 170 #define RAMCTL_REGS_TXFIFO_2_LEVEL                         0x002
 171 #define RAMCTL_REGS_TXFIFO_3_LEVEL                         0x003
 172 #define RAMCTL_REGS_RXFIFO_0_LEVEL                         0x004
 173
 174 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_M                 0x7ff
 175 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL_S                 0
 176 #define RAMCTL_REGS_RXFIFO_0_LEVEL_LEVEL                   0x7ff
 177 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_M                 0x1
 178 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE_S                 11
 179 #define RAMCTL_REGS_RXFIFO_0_LEVEL_STALE                   0x800
 180
 181 #define RAMCTL_REGS_RXFIFO_1_LEVEL                         0x005
 182 #define RAMCTL_REGS_RXFIFO_2_LEVEL                         0x006
 183 #define RAMCTL_REGS_RXFIFO_3_LEVEL                         0x007
 184
 185 #define RAMCTL_BUFFER_PARITY                               0x1
 186 #define RAMCTL_BUFFER_BREAK                                0x2
 187 #define RAMCTL_BUFFER_FRAME                                0x4
 188 #define RAMCTL_BUFFER_OVERRUN                              0x8
 189
 190 #ifndef CMSPAR
 191 #define CMSPAR                  0
 192 #endif
 193
 194 /*
 195  * Major and minor numbers.
 196  */
 197
 198 #define XR21V141X_TTY_MAJOR             166
 199 #define XR21V141X_TTY_MINORS            32
 200
 201 #define USB_RT_ACM              (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
 202
 203 #define ACM_CTRL_DTR            0x01
 204 #define ACM_CTRL_RTS            0x02
 205 #define ACM_CTRL_DCD            0x01
 206 #define ACM_CTRL_DSR            0x02
 207 #define ACM_CTRL_BRK            0x04
 208 #define ACM_CTRL_RI             0x08
 209
 210 #define ACM_CTRL_FRAMING        0x10
 211 #define ACM_CTRL_PARITY         0x20
 212 #define ACM_CTRL_OVERRUN        0x40
 213
 214 /*
 215  * Internal driver structures.
 216  */
 217
 218 #define ACM_NW  16
 219 #define ACM_NR  16
 220
 221 struct xr21v141x_wb {
 222         unsigned char *buf;
 223         dma_addr_t dmah;
 224         int len;
 225         int use;
 226         struct urb              *urb;
 227         struct xr21v141x        *instance;
 228 };
 229
 230 struct xr21v141x_rb {
 231         int                     size;
 232         unsigned char           *base;
 233         dma_addr_t              dma;
 234         int                     index;
 235         struct xr21v141x        *instance;
 236 };
 237
 238 struct xr21v141x {
 239         struct usb_device *dev;                         /* the corresponding usb device */
 240         struct usb_interface *control;                  /* control interface */
 241         struct usb_interface *data;                     /* data interface */
 242         struct tty_port port;                           /* our tty port data */
 243         struct urb *ctrlurb;                            /* urbs */
 244         u8 *ctrl_buffer;                                /* buffers of urbs */
 245         dma_addr_t ctrl_dma;                            /* dma handles of buffers */
 246         u8 *country_codes;                              /* country codes from device */
 247         unsigned int country_code_size;                 /* size of this buffer */
 248         unsigned int country_rel_date;                  /* release date of version */
 249         struct xr21v141x_wb wb[ACM_NW];
 250         unsigned long read_urbs_free;
 251         struct urb *read_urbs[ACM_NR];
 252         struct xr21v141x_rb read_buffers[ACM_NR];
 253         int rx_buflimit;
 254         int rx_endpoint;
 255         spinlock_t read_lock;
 256         int write_used;                                 /* number of non-empty write buffers */
 257         int transmitting;
 258         spinlock_t write_lock;
 259         struct mutex mutex;
 260         bool disconnected;
 261         struct usb_cdc_line_coding line;                /* bits, stop, parity */
 262         struct work_struct work;                        /* work queue entry for line discipline waking up */
 263         unsigned int ctrlin;                            /* input control lines (DCD, DSR, RI, break, overruns) */
 264         unsigned int ctrlout;                           /* output control lines (DTR, RTS) */
 265         unsigned int writesize;                         /* max packet size for the output bulk endpoint */
 266         unsigned int readsize,ctrlsize;                 /* buffer sizes for freeing */
 267         unsigned int minor;                             /* acm minor number */
 268         unsigned char clocal;                           /* termios CLOCAL */
 269         unsigned int ctrl_caps;                         /* control capabilities from the class specific header */
 270         unsigned int susp_count;                        /* number of suspended interfaces */
 271         unsigned int combined_interfaces:1;             /* control and data collapsed */
 272         unsigned int is_int_ep:1;                       /* interrupt endpoints contrary to spec used */
 273         unsigned int throttled:1;                       /* actually throttled */
 274         unsigned int throttle_req:1;                    /* throttle requested */
 275         u8 bInterval;
 276         struct xr21v141x_wb *delayed_wb;                        /* write queued for a device about to be woken
 277  */
 278         int           block;
 279         int           preciseflags; /* USB: wide mode, TTY: flags per character */
 280         int           trans9;   /* USB: wide mode, serial 9N1 */
 281
 282 #ifdef VIZZINI_IWA
 283         int           iwa;
 284 #endif
 285
 286 };
 287
 288 #define CDC_DATA_INTERFACE_TYPE 0x0a
 289 /* constants describing various quirks and errors */
 290 #define NO_UNION_NORMAL                 1
 291 #define SINGLE_RX_URB                   2
 292 #define NO_CAP_LINE                     4
 293 #define NOT_A_MODEM                     8
 294 #define NO_DATA_INTERFACE               16
 295
 296 #endif /*VIZZINI_H*/